Datasheet

Section 16 LPC Interface (LPC)
Rev. 3.00 Sep. 28, 2009 Page 421 of 710
REJ09B0384-0300
16.3.5 LPC Channel 3 Address Register H, L (LADR3H, LADR3L)
LADR3 comprises two 8-bit readable/writable registers that perform LPC channel 3 host address
setting and control the operation of the bidirectional data registers. The contents of the address
field in LADR3 must not be changed while channel 3 is operating (while LPC3E is set to 1).
• LADR3H
R/W
Bit Bit Name Initial Value Slave Host Description
7
6
5
4
3
2
1
0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
All 0 R/W ⎯ Channel 3 Address Bits 15 to 8
The host address of LPC channel 3 is set.
• LADR3L
R/W
Bit Bit Name Initial Value Slave Host Description
7
6
5
4
3
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
All 0 R/W ⎯ Channel 3 Address Bits 7 to 3
The host address of LPC channel 3 is set.
2 ⎯ 0 R/W ⎯ Reserved
The initial value should not be changed.
1 Bit 1 0 R/W ⎯ Channel 3 Address Bit 1
The host address of LPC channel 3 is set.
0 TWRE 0 R/W ⎯ Bidirectional Data Register Enable
Enables or disables bidirectional data register
operation.
Clear this bit to 0 in KCS mode.
0: TWR operation is disabled
TWR-related address (LADR3) match does not
occur.
1: TWR operation is enabled