Datasheet

Section 16 LPC Interface (LPC)

Rev. 3.00 Sep. 28, 2009 Page 420 of 710

REJ09B0384-0300

Table 16.2 LADR1, LADR2 Initial Values

LADR1 H'0060 I/O address of channel 1

LADR2 H'0062 I/O address of channel 2

Table 16.3 Host Register Selection

I/O Address

Bits 15 to 3 Bit 2 Bit 1 Bit 0

Transfer

Cycle Host Register Selection

LADR1 (bits 15 to 3) 0 LADR1 (bit 1) LADR1 (bit 0) I/O write IDR1 write (data),

C/D1 ← 0

LADR1 (bits 15 to 3) 1 LADR1 (bit 1) LADR1 (bit 0) I/O write IDR1 write (command),

C/D1 ← 1

LADR1 (bits 15 to 3) 0 LADR1 (bit 1) LADR1 (bit 0) I/O read ORD1 read

LADR1 (bits 15 to 3) 1 LADR1 (bit 1) LADR1 (bit 0) I/O read STR1 read

LADR2 (bits 15 to 3) 0 LADR2 (bit 1) LADR2 (bit 0) I/O write IDR2 write (data),

C/D2 ← 0

LADR2 (bits 15 to 3) 1 LADR2 (bit 1) LADR2 (bit 0) I/O write IDR2 write (command),

C/D2 ← 1

LADR2 (bits 15 to 3) 0 LADR2 (bit 1) LADR2 (bit 0) I/O read ODR2 read

LADR2 (bits 15 to 3) 1 LADR2 (bit 1) LADR2 (bit 0) I/O read STR2 read

Table 16.4 Slave Selection Internal Registers

Slave (R/W) Bus Width (B/W) LADR12SEL LADR12 Internal Register

R/W B 0 LADR12H LADR1H

R/W B 1 LADR12H LADR2H

R/W B 0 LADR12L LADR1L

R/W B 1 LADR12L LADR2L

R/W W 0 LADR12H LADR12L LADR1H LADR1L

R/W W 1 LADR12H LADR12L LADR2H LADR2L