Datasheet

Section 16 LPC Interface (LPC)
Rev. 3.00 Sep. 28, 2009 Page 418 of 710
REJ09B0384-0300
16.3.3 Host Interface Control Register 4 (HICR4)
HICR4 controls the operation of the KCS, SMIC, and BT interface functions on channel 3.
R/W
Bit Bit Name Initial Value Slave Host Description
7 LADR12SEL 0 R/W ⎯ Switches the channel accessed via LADR12H and
LADR12L.
0: LADR1 is selected
1: LADR2 is selected
6 ⎯ 0 R/W ⎯ Reserved
The initial value should not be changed.
5 CH2OFFSEL 0 R/W ⎯ Channel 2 Offset
Selects the address offset for LPC channel 2.
0: Offset 4
1: Offset 1
4 CH1OFFSEL 0 R/W ⎯ Channel 1 Offset
Selects the address offset for LPC channel 1.
0: Offset 4
1: Offset 1
3 SWENBL 0 R/W ⎯ In BT mode, H’5 (short wait) or H’6 (long wait) is
returned to the host in the synchronized return
cycle from slave, thus can make the host wait.
0: Short wait is issued
1: Long wait is issued
2 KCSENBL 0 R/W ⎯ Enables or disables the use of the KCS interface
included in channel 3. When the LPC3E bit in
HICR0 is 0, this bit is valid.
0: KCS interface operation is disabled
No address (LADR3) matches for IDR3, ODR3,
or STR3 in KCS mode
1: KCS interface operation is enabled