Datasheet

Section 16 LPC Interface (LPC)
Rev. 3.00 Sep. 28, 2009 Page 417 of 710
REJ09B0384-0300
R/W
Bit Bit Name
Initial
Value
Slave Host Description
0 ERRIE 0 R/W ⎯ Error Interrupt Enable
Enables or disables ERRI interrupt to the slave (this
LSI).
0: Error interrupt requests disabled
1: Error interrupt requests enabled
Note: * Only 0 can be written to bits 6 to 4, to clear the flag.
• HICR3
R/W
Bit Bit Name Initial Value Slave Host Description
7 LFRAME Undefined R ⎯ 0: LFRAME Pin state is low level
1: LFRAME Pin state is high level
6 ⎯ Undefined R ⎯ Reserved
5 SERIRQ Undefined R ⎯ 0: SERIRQ Pin state is low level
1: SERIRQ Pin state is high level
4 LRESET Undefined R ⎯ 0: LRESET Pin state is low level
1: LRESET Pin state is high level
3 ⎯ Undefined R ⎯ Reserved
2 ⎯ Undefined R ⎯ Reserved
1 ⎯ Undefined R ⎯ Reserved
0 ⎯ Undefined R ⎯ Reserved