Datasheet

Section 16 LPC Interface (LPC)
Rev. 3.00 Sep. 28, 2009 Page 416 of 710
REJ09B0384-0300
R/W
Bit Bit Name
Initial
Value Slave Host
Description
3 IBFIE3 0 R/W ⎯ IDR3 and TWR Receive Complete interrupt Enable
Enables or disables IBFI3 interrupt to the slave (this
LSI).
0: Input data register (IDR3) and TWR receive
complete interrupt requests and SMIC/BT mode
interrupt requests disabled
1: [When TWRIE = 0 in LADR3]
Input data register (IDR3) receive complete
interrupt requests and SMIC/BT mode
interrupt requests enabled
[When TWRIE = 1 in LADR3]
Input data register (IDR3) and TWR receive
complete interrupt requests and SMIC/BT
mode interrupt requests enabled
2 IBFIE2 0 R/W ⎯ IDR2 Receive Complete Interrupt Enable
Enables or disables IBFI2 interrupt to the slave (this
LSI).
0: Input data register (IDR2) receive complete
interrupt requests disabled
1: Input data register (IDR2) receive complete
interrupt requests enabled
1 IBFIE1 0 R/W ⎯ IDR1 Receive Complete Interrupt Enable
Enables or disables IBFI1 interrupt to the slave (this
LSI).
0: Input data register (IDR1) receive complete
interrupt requests disabled
1: Input data register (IDR1) receive complete
interrupt requests enabled