Datasheet

Section 16 LPC Interface (LPC)
Rev. 3.00 Sep. 28, 2009 Page 415 of 710
REJ09B0384-0300
16.3.2 Host Interface Control Registers 2 and 3 (HICR2 and HICR3)
HICR2 controls interrupts to an LPC interface slave (this LSI). HICR3 monitors the states of the
LPC interface pins. Bits 6 to 0 in HICR2 are initialized to H'00 by a reset. The states of other bits
are decided by the pin states. The pin states can be monitored by the pin monitoring bits regardless
of the LPC interface operating state or the operating state of the functions that use pin
multiplexing.
• HICR2
R/W
Bit Bit Name
Initial
Value Slave Host
Description
7 ⎯ Undefined R ⎯ Reserved
6 LRST 0 R/(W)* ⎯ LPC Reset Interrupt Flag
This bit is a flag that generates an ERRI interrupt
when an LPC hardware reset occurs.
0: [Clearing condition]
Writing 0 after reading LRST = 1
1: [Setting condition]
LRESET pin falling edge detection
5 ⎯ 0 R/(W)* ⎯ Reserved
The initial value should not be changed.
4 ABRT 0 R/(W)* ⎯ LPC Abort Interrupt Flag
This bit is a flag that generates an ERRI interrupt
when a forced termination (abort) of an LPC transfer
cycle occurs.
0: [Clearing conditions]
• Writing 0 after reading ABRT = 1
• LPC hardware reset
(LRESET pin falling edge detection)
• LPC software reset (LRSTB = 1)
• LPC software shutdown (SDWNB = 1)
1: [Setting condition]
LFRAME pin falling edge detection during LPC
transfer cycle