Datasheet

ManualsBrandsRENESAS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LFBGA 112 (10x10) 16-Bit 25 MHz I/O number 53

Section 16 LPC Interface (LPC)

Rev. 3.00 Sep. 28, 2009 Page 409 of 710

REJ09B0384-0300

The following registers are necessary for SMIC mode

• SMIC flag register (SMICFLG)

• SMIC control/status register (SMICCSR)

• SMIC data register (SMICDTR)

• SMIC interrupt register 0 (SMICIR0)

• SMIC interrupt register 1 (SMICIR1)

The following registers are necessary for BT mode

• BT status register 0 (BTSR0)

• BT status register 1 (BTSR1)

• BT control/status register 0 (BTCSR0)

• BT control/status register 1 (BTCSR1)

• BT control register (BTCR)

• BT data buffer (BTDTR)

• BT interrupt mask register (BTIMSR)

• FIFO valid size register 0 (BTFVSR0)

• FIFO valid size register 1 (BTFVSR1)