Datasheet

Section 16 LPC Interface (LPC)
Rev. 3.00 Sep. 28, 2009 Page 407 of 710
REJ09B0384-0300
16.2 Input/Output Pins
Table 16.1 lists the LPC pin configuration.
Table 16.1 Pin Configuration
Name Abbreviation Port I/O Function
LPC address/
data 3 to 0
LAD3 to LAD0 PE to PE0 I/O Cycle type/address/data signals
serially (4-signal-line) transferred in
synchronization with LCLK
LPC frame LFRAME PE4 Input* Transfer cycle start and forced
termination signal
LPC reset LRESET PE5 Input* LPC interface reset signal
LPC clock LCLK PE6 Input 33-MHz PCI clock signal
Serialized
interrupt request
SERIRQ PE7 I/O* Serialized host interrupt request
signal (SMI, HIRQ1 to HIRQ15) in
synchronization with LCLK
Note: * Pin state monitoring input is possible in addition to the LPC interface control
input/output function.