Datasheet

Section 16 LPC Interface (LPC)
Rev. 3.00 Sep. 28, 2009 Page 405 of 710
REJ09B0384-0300
Section 16 LPC Interface (LPC)
This LSI has an on-chip LPC interface.
The LPC includes three register sets, each of which comprises data and status registers, control
register, and the host interrupt request circuit.
The LPC performs serial transfer of cycle type, address, and data, synchronized with the 33 MHz
PCI clock. It uses four signal lines for address/data and one for host interrupt requests. This LPC
module supports I/O read and I/O write cycle transfers.
16.1 Features
• Supports LPC interface I/O read and I/O write cycles
⎯ Uses four signal lines (LAD3 to LAD0) to transfer the cycle type, address, and data.
⎯ Uses three control signals: clock (LCLK), reset (LRESET), and frame (LFRAME).
• Three register sets comprising data and status registers
⎯ The basic register set comprises three bytes: an input register (IDR), output register (ODR),
and status register (STR).
⎯ I/O addresses from H'0000 to H'FFFF are selected for channels 1 to 3.
⎯ For channel 3, sixteen bidirectional data register bytes can be manipulated in addition to
the basic register set.
• Supports SERIRQ
⎯ Host interrupt requests are transferred serially on a single signal line (SERIRQ).
⎯ On channel 1, HIRQ1 and HIRQ12 can be generated.
⎯ On channels 2 and 3, SMI, HIRQ6, and HIRQ9 to HIRQ11 can be generated.
⎯ Operation can be switched between quiet mode and continuous mode.
• Supports version 1.5 of the Intelligent Platform Management Interface (IPMI) specifications
⎯ Channel 3 supports the SMIC interface, KCS interface, and BT interface.