Datasheet

Section 15 I
2
C Bus Interface (IIC)
Rev. 3.00 Sep. 28, 2009 Page 404 of 710
REJ09B0384-0300
S
S
S
A
A
A
A
A
SLA
SLA
SLA
DATA1
DATA2
SLA
R/W
R/W
R/W
R/W
A
DATA3
A
DATA4
I2C bus interface
(Master transmit mode)
Transmit data match
Transmit timing match
• Receive address is ignored • Automatically transferred to slave
receive mode
• Receive data is recognized as an
address
• When the receive data matches to
the address set in the SAR or SARX
register, the I2C bus interface operates
as a slave device.
• Arbitration is lost
• The AL flag in ICSR is set to 1
Transmit data does not match
Data contention
Other device
(Master transmit mode)
I2C bus interface
(Slave receive mode)
Figure 15.35 Diagram of Erroneous Operation when Arbitration Lost
Though it is prohibited in the normal I
2
C protocol, the same problem may occur when the MST
bit is erroneously set to 1 and a transition to master mode is occurred during data transmission
or reception in slave mode.
When the MST bit is set to 1 during data transmission or reception in slave mode, the
arbitration decision circuit is enabled and arbitration is lost if conditions are satisfied. In this
case, the transmit/receive data which is not an address may be erroneously recognized as an
address.
In multi-master mode, pay attention to the setting of the MST bit when a bus conflict may
occur. In this case, the MST bit in the ICCR register should be set to 1 according to the order
below.
A. Make sure that the BBSY flag in the ICCR register is 0 and the bus is free before setting
the MST bit.
B. Set the MST bit to 1.
C. To confirm that the bus was not entered to the busy state while the MST bit is being set,
check that the BBSY flag in the ICCR register is 0 immediately after the MST bit has been
set.
Note: Above restrictions can be released by setting the bits FNC1 and FNC2 in ICXR to B'11.