Datasheet

Section 15 I
2
C Bus Interface (IIC)
Rev. 3.00 Sep. 28, 2009 Page 402 of 710
REJ09B0384-0300
Restart condition
Data
transmission
Address reception
SCL
TRS
TRS bit setting is suspended in this period
ICDR dummy read
TRS bit setting
(a) (b)
8
A
9 123 456789
The rise of the 9th clock is detected
SDA
The rise of the 9th clock is detected
Figure 15.34 TRS Bit Set Timing in Slave Mode
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B′11 in
ICXR.
13. Note on ICDR read in transmit mode and ICDR write in receive mode
When ICDR is read in transmit mode (TRS = 1) or ICDR is written to in receive mode (TRS =
0), the SCL pin may not be held low in some cases after transmit/receive operation has been
completed, thus inconveniently allowing clock pulses to be output on the SCL bus line before
ICDR is accessed correctly. To access ICDR correctly, read the ICDR after setting receive
mode or write to the ICDR after setting transmit mode.