Datasheet

Section 15 I
2
C Bus Interface (IIC)
Rev. 3.00 Sep. 28, 2009 Page 399 of 710
REJ09B0384-0300
9. Note on when I
2
C bus interface stop condition instruction is issued
In a situation where the rise time of the 9th clock of SCL exceeds the stipulated value because
of a large bus load capacity or where a slave device in which a wait can be inserted by driving
the SCL pin low is used, the stop condition instruction should be issued after reading SCL after
the rise of the 9th clock pulse and determining that it is low.
Stop condition generation
SCL
IRIC
[1] SCL = low determination
VIH
[2] Stop condition instruction issuance
SDA
9th clock
Secures a high period
SCL is detected as low
because the rise of the
waveform is delayed
Figure 15.31 Stop Condition Issuance Timing
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B′11 in
ICXR.
10. Note on IRIC flag clear when the wait function is used
When the wait function is used in I
2
C bus interface master mode and in a situation where the
rise time of SCL exceeds the stipulated value or where a slave device in which a wait can be
inserted by driving the SCL pin low is used, the IRIC flag should be cleared after determining
that the SCL is low.
If the IRIC flag is cleared to 0 when WAIT = 1 while the SCL is extending the high level time,
the SDA level may change before the SCL goes low, which may generate a start or stop
condition erroneously.