Datasheet

Section 15 I

C Bus Interface (IIC)

Rev. 3.00 Sep. 28, 2009 Page 397 of 710

REJ09B0384-0300

SDA

SCL

Internal clock

BBSY bit

Master receive mode

ICDR read

disabled period

Bit 0

Stop condition

(a)

Start condition

Execution of instruction

for issuing stop condition

(write 0 to BBSY and SCP)

Confirmation of stop

condition issuance

(read BBSY = 0)

Start condition

issuance

Figure 15.29 Notes on Reading Master Receive Data

Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B′11 in

ICXR.

8. Notes on start condition issuance for retransmission

Figure 15.30 shows the timing of start condition issuance for retransmission, and the timing for

subsequently writing data to ICDR, together with the corresponding flowchart. Write the

transmit data to ICDR after the start condition for retransmission is issued and then the start

condition is actually generated.