Datasheet

Section 15 I
2
C Bus Interface (IIC)
Rev. 3.00 Sep. 28, 2009 Page 395 of 710
REJ09B0384-0300
Table 15.13 I
2
C Bus Timing (with Maximum Influence of t
Sr
/t
Sf
)
Time Indication (at Maximum Transfer Rate) [ns]
Item
t
cyc
Indication
t
Sr
/t
Sf
Influence
(Max.)
I
2
C Bus
Specification
(Min.)
φ = 20 MHz φ = 25 MHz
⎯ ⎯ Standard mode ⎯ ⎯ φ/200 φ/224
⎯ ⎯ High-speed mode ⎯ ⎯ φ/48 φ/56
t
SCLHO
Standard mode –1000 4000 4000 3480
0.5 t
SCLO
(–t
Sr
)
High-speed mode 300 600 900 820
t
SCLLO
Standard mode –250 4700 4750 4230
0.5 t
SCLO
(–t
Sf
)
High-speed mode –250 1300 950*
1
870*
1
t
BUFO
Standard mode –1000 4700 3950*
1
3440*
1
0.5 t
SCLO
–1 t
cyc
( –t
Sr
)
High-speed mode –300 1300 850*
1
780*
1
t
STAHO
Standard mode –250 4000 4700 4190
0.5 t
SCLO
–1 t
cyc
(–t
Sf
)
High-speed mode –250 600 900 830
t
STASO
Standard mode –1000 4700 9000 7960
1 t
SCLO
(–t
Sr
)
High-speed mode –300 600 2100 1940
t
STOSO
Standard mode –1000 4000 4100 3560
0.5 t
SCLO
+ 2 t
cyc
(–t
Sr
)
High-speed mode 300 600 1000 900
Standard mode –1000 250 3600 3100 t
SDASO
(master)
1 t
SCLLO
*
3
–3 t
cyc
(–t
Sr
)
High-speed mode –300 100 500 450
Standard mode –1000 250 3100 3220 t
SDASO
(slave)
1 t
SCLL
*
3
–12 t
cyc
*
2
(–t
Sr
)
High-speed mode –300 100 400 520
t
SDAHO
3 t
cyc
Standard mode 0 0 150 120
High-speed mode 0 0 150 120
Notes: 1. Does not meet the I
2
C bus interface specification. Remedial action such as the following
is necessary: (a) secure a start/stop condition issuance interval; (b) adjust the rise and
fall times by means of a pull-up resistor and capacitive load; (c) reduce the transfer rate;
(d) select slave devices whose input timing permits this output timing.
The values in the above table will vary depending on the settings of the bits TCSS,
IICX3 to IICX0 and CKS2 to CKS0. Depending on the frequency it may not be possible
to achieve the maximum transfer rate; therefore, whether or not the I
2
C bus interface
specifications are met must be determined in accordance with the actual setting
conditions.
2. Value when the IICXn bit is set to 1. When the IICXn bit is cleared to 0, the value is
(– 6t
cyc
) (n = 0 to 3).