Datasheet

Section 15 I
2
C Bus Interface (IIC)
Rev. 3.00 Sep. 28, 2009 Page 393 of 710
REJ09B0384-0300
4. SCL and SDA input are sampled in synchronization with the internal clock. The AC timing
therefore depends on the system clock cycle t
cyc
, as shown in section 24, Electrical
Characteristics. Note that the I
2
C bus interface AC timing specification will not be met with a
system clock frequency of less than 5 MHz.
5. The I
2
C bus interface specification for the SCL rise time t
sr
is 1000 ns or less (300 ns for high-
speed mode). In master mode, the I
2
C bus interface monitors the SCL line and synchronizes
one bit at a time during communication. If t
sr
(the time for SCL to go from low to V
IH
) exceeds
the time determined by the input clock of the I
2
C bus interface, the high period of SCL is
extended. The SCL rise time is determined by the pull-up resistance and load capacitance of
the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance
and load capacitance so that the SCL rise time does not exceed the values given in table 15.12.
Table 15.12 Permissible SCL Rise Time (t
sr
) Values
Time Indication [ns]
TCSS IICXn
t
cyc
Indi-
cation
I
2
C Bus
Specification
(Max.)
φ = 20
MHz
φ = 25
MHz
Standard mode 1000 375 300 0 7.5 t
cyc
High-speed mode 300 300 300
0
1 Standard mode 1000 875 700
1 0
17.5 t
cyc
High-speed mode 300 300 300
1 1 37.5 t
cyc
Standard mode 1000 1000 1000
High-speed mode 300 300 300
[Legend] n = 0 to 3
6. The I
2
C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns
and 300 ns. The I
2
C bus interface SCL and SDA output timing is prescribed by t
cyc
, as shown in
table 15.11. However, because of the rise and fall times, the I
2
C bus interface specifications
may not be satisfied at the maximum transfer rate. Table 15.13 shows output timing
calculations for different operating frequencies, including the worst-case influence of rise and
fall times.
t
BUFO
fails to meet the I
2
C bus interface specifications at any frequency. The solution is either (a)
to provide coding to secure the necessary interval (approximately 1 µs) between issuance of a
stop condition and issuance of a start condition, or (b) to select devices whose input timing
permits this output timing for use as slave devices connected to the I
2
C bus.