Datasheet
Section 15 I
2
C Bus Interface (IIC)
Rev. 3.00 Sep. 28, 2009 Page 392 of 710
REJ09B0384-0300
15.6 Usage Notes
1. In master mode, if an instruction to generate a start condition is immediately followed by an
instruction to generate a stop condition, neither condition will be output correctly. To output
consecutive start and stop conditions*, after issuing the instruction that generates the start
condition, read the relevant DR registers of I
2
C bus output pins, check that SCL and SDA are
both low. If the ICE bit is set to 1, pin state can be monitored by reading DR register. Then
issue the instruction that generates the stop condition. Note that SCL may not yet have gone
low when BBSY is cleared to 0.
Note: * An illegal procedure in the I
2
C bus specification.
2. Either of the following two conditions will start the next transfer. Pay attention to these
conditions when accessing to ICDR.
⎯ Write to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from ICDRT to
ICDRS)
⎯ Read from ICDR when ICE = 1 and TRS = 0 (including automatic transfer from ICDRS to
ICDRR)
3. Table 15.11 shows the timing of SCL and SDA outputs in synchronization with the internal
clock. Timings on the bus are determined by the rise and fall times of signals affected by the
bus load capacitance, series resistance, and parallel resistance.
Table 15.11 I
2
C Bus Timing (SCL and SDA Outputs)
Item Symbol Output Timing Unit Notes
SCL output cycle time t
SCLO
28t
cyc
to 512t
cyc
ns
SCL output high pulse width t
SCLHO
0.5t
SCLO
ns
SCL output low pulse width t
SCLLO
0.5t
SCLO
ns
SDA output bus free time t
BUFO
0.5t
SCLO
– 1t
cyc
ns
Start condition output hold time t
STAHO
0.5t
SCLO
– 1t
cyc
ns
Retransmission start condition output
setup time
t
STASO
1t
SCLO
ns
Stop condition output setup time t
STOSO
0.5t
SCLO
+ 2t
cyc
ns
Data output setup time (master) 1t
SCLLO
– 3t
cyc
Data output setup time (slave)
t
SDASO
1t
SCLLO
– (6t
cyc
or 12t
cyc
*)
ns
See figure
24.18
(reference)
Data output hold time t
SDAHO
3t
cyc
ns
Note: * 6t
cyc
when IICXn is 0, 12t
cyc
when IICXn is 1 (n = 0 to 3).