Datasheet

Section 15 I
2
C Bus Interface (IIC)
Rev. 3.00 Sep. 28, 2009 Page 380 of 710
REJ09B0384-0300
Stop condition detection
SDA
(master output)
SDA
(slave output)
21436521436587987989
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 1 Bit 0
ICDRF
ICDRS
ICDRR
IRIC
SCL
(master output)
[9] Set ACKB = 1
[13] IRIC clear
[10] ICDR read
(Data (n-2))
[10] ICDR read
(Data (n-1))
[13] IRIC clear
[9] Wait for one frame
User processing
Bit 7Bit 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
Data (n)
Data (n-1)
Data (n-1)
Data (n-1)
Data (n-2)
Data (n-2)
Data (n)
Data (n)
Data (n-2)
[11]
[11]
[11] [12]
AA A
[13] IRIC clear
[14] ICDR read
(Data (n))
[15] IRIC clear
Figure 15.22 Slave Receive Mode Operation Timing Example (2)
(MLS = ACKB = 0, HNDS = 0)