Datasheet

Section 15 I
2
C Bus Interface (IIC)
Rev. 3.00 Sep. 28, 2009 Page 376 of 710
REJ09B0384-0300
SDA
(master output)
SDA
(slave output)
21 214365879
Bit 7 Bit 6 Bit 7 Bit 6Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ICDRF
IRIC
ICDRS
ICDRR
SCL
(master output)
SCL
(slave output)
Address
+R/W
Address
+R/W
Undefined value
[8] IRIC clear [10] ICDR read (dummy read)
User processing
21 214365879
SCL
(Pin waveform)
Start condition generation
Slave address
Data 1
[6]
A
R/W
[7] SCL is fixed low until ICDR is read
[2] ICDR read
Interrupt
request
occurrence
Figure 15.18 Slave Receive Mode Operation Timing Example (1) (MLS = 0, HNDS= 1)
SDA
(master output)
SDA
(slave output)
21436587989
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 0
IRIC
ICDRS
ICDRF
ICDRR
Data (n-1)
SCL
(master output)
SCL
(slave output)
[8] IRIC clear
[12] IRIC clear
[9] Set ACKB=1
[10] ICDR read (
Data (n-
1))
[10] ICDR read
(
Data (n
))
User processing
Data (n
)
Data (n-
1)
Data (n-2
)
[6] [6]
[11]
A A
Stop condition generation
[7] SCL is fixed low until ICDR is read
[7] SCL is fixed low until ICDR is read
Data (n-
1)
Data (n
)
Data (n
)
[8] IRIC clear
Figure 15.19 Slave Receive Mode Operation Timing Example (2) (MLS = 0, HNDS= 1)