Datasheet

Section 15 I
2
C Bus Interface (IIC)
Rev. 3.00 Sep. 28, 2009 Page 373 of 710
REJ09B0384-0300
SDA
(master output)
SDA
(slave output)
21
4
3
65
8
7
998
A
A
Bit 7Bit 0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
IRIC
IRTR
ICDR
SCL
(master output)
Data 3
Data 2
Data 1 Data 2
Data 3
[6] IRIC clear
(to end wait
insertion)
[8] Wait for one clock pulse
[11] IRIC clear
[14] IRIC clear
(to end wait
insertion)
[16] ICDR read
(Data 3)
User processing
[12]
[3]
[10] ICDR read (Data 2)
[9]
Set TRS=1
[7] Set ACKB=1
[15] WAIT cleared to 0,
IRIC clear
[17] Stop condition issuance
Bit 0
Stop condition generation
[13] IRTR=1
[13] IRTR=0
[12]
[4] IRTR=1
[4] IRTR=0
[3]
Figure 15.16 Stop Condition Issuance Timing Example in Master Receive Mode
(MLS = ACKB = 0, WAIT = 1)
15.4.5 Slave Receive Operation
In I
2
C bus format slave receive mode, the master device outputs the transmit clock and transmit
data, and the slave device returns an acknowledge signal.
The slave device operates as the device specified by the master device when the slave address in
the first frame following the start condition that is issued by the master device matches its own
address.