Datasheet

Section 15 I
2
C Bus Interface (IIC)
Rev. 3.00 Sep. 28, 2009 Page 357 of 710
REJ09B0384-0300
15.3.9 I
2
C SMBus Control Register (ICSMBCR)
ICSMBCR is used to support the System Management Bus (SMBus) specifications. To support
the SMBus specification, SDA output data hold time should be specified in the range of 300 ns to
1000 ns. Table 15.6 shows the relationship between the ICSMBCR setting and output data hold
time.
When the SMBus is not supported, the initial value should not be changed. ICSMBCR is enabled
to access when bit MSTP4 is cleared to 0.
Bit Bit Name
Initial
Value
R/W Description
7
6
⎯
⎯
⎯
⎯
⎯
⎯
Reserved
These bits cannot be modified. The read values are
undefined.
5
4
3
2
SMB3E
SMB2E
SMB1E
SMB0E
All 0 R/W SMBus Enable
These bits enable/disable to support the SMBus,
combining with bits FSEL1 and FSEL0. The SMB3E bit
controls IIC_3, the SMB2E bit controls IIC_2, the SMB1E
bit controls IIC_1, the SMB0E bit controls IIC_0.
0: Disables to support the SMBus
1: Enables to support the SMBus
1
0
FSEL1
FSEL0
0
0
R/W
R/W
Frequency Selection
These bits must be specified to match the system clock
frequency in order to support the SMBus. For details of the
setting, see table 15.7.