Datasheet

Section 15 I
2
C Bus Interface (IIC)
Rev. 3.00 Sep. 28, 2009 Page 341 of 710
REJ09B0384-0300
Bit Bit Name
Initial
Value
R/W Description
5
4
MST
TRS
0
0
R/W
R/W
[MST clearing conditions]
(1) When 0 is written by software
(2) When lost in bus contention in I
2
C bus format master
mode
[MST setting conditions]
(1) When 1 is written by software (for MST clearing
condition 1)
(2) When 1 is written in MST after reading MST = 0 (for
MST clearing condition 2)
[TRS clearing conditions]
(1) When 0 is written by software (except for TRS setting
condition 3)
(2) When 0 is written in TRS after reading TRS = 1 (for
TRS setting condition 3)
(3) When lost in bus contention in I
2
C bus format master
mode
[TRS setting conditions]
(1) When 1 is written by software (except for TRS clearing
condition 3)
(2) When 1 is written in TRS after reading TRS = 0 (for
TRS clearing condition 3)
(3) When 1 is received as the R/W bit after the first frame
address matching in I
2
C bus format slave mode
3 ACKE 0 R/W Acknowledge Bit Decision Selection
0: The value of the acknowledge bit is ignored, and
continuous transfer is performed. The value of the
received acknowledge bit is not indicated by the ACKB
bit in ICSR, which is always 0.
1: If the acknowledge bit is 1, continuous transfer is
halted.
Depending on the receiving device, the acknowledge bit
may be significant, in indicating completion of processing
of the received data, for instance, or may be fixed at 1 and
have no significance.