Datasheet

Section 15 I
2
C Bus Interface (IIC)
Rev. 3.00 Sep. 28, 2009 Page 340 of 710
REJ09B0384-0300
15.3.6 I
2
C Bus Control Register (ICCR)
ICCR controls the I
2
C bus interface and performs interrupt flag confirmation.
Bit Bit Name
Initial
Value
R/W Description
7 ICE 0 R/W I
2
C Bus Interface Enable
0: I
2
C bus interface modules are stopped and I
2
C bus
interface module internal state is initialized. SAR and
SARX can be accessed.
1: I
2
C bus interface modules can perform transfer and
reception, they are connected to the SCL and SDA pins,
and the I
2
C bus can be driven. ICMR and ICDR can be
accessed.
6 IEIC 0 R/W I
2
C Bus Interface Interrupt Enable
0: Disables interrupts from the I
2
C bus interface to the
CPU.
1: Enables interrupts from the I
2
C bus interface to the
CPU.
5
4
MST
TRS
0
0
R/W
R/W
Master/Slave Select
Transmit/Receive Select
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
Both these bits will be cleared by hardware when they
lose in a bus contention in master mode of the I
2
C bus
format. In slave receive mode with I
2
C bus format, the R/W
bit in the first frame immediately after the start condition
automatically sets these bits in receive mode or transmit
mode by hardware.
Modification of the TRS bit during transfer is deferred until
transfer is completed, and the changeover is made after
completion of the transfer.