Datasheet

Section 1 Overview
Rev. 3.00 Sep. 28, 2009 Page 1 of 710
REJ09B0384-0300
Section 1 Overview
1.1 Overview
• High-speed H8S/2600 central processing unit with an internal 16-bit architecture
Upward-compatible with H8/300 and H8/300H CPUs on an object level
Sixteen 16-bit general registers
69 basic instructions
Multiplication and accumulation instructions
• Various peripheral functions
Data transfer controller (DTC)
14-bit PWM timer (PWMX)
16-bit free-running timer (FRT)
8-bit timer (TMR)
Watchdog timer (WDT)
Asynchronous or clocked synchronous serial communication interface (SCI)
CRC operation circuit (CRC)
I
2
C bus interface (IIC)
LPC interface (LPC)
10-bit A/D converter
Boundary scan (JTAG)
Clock pulse generator
• On-chip memory
ROM Type Model ROM RAM Remarks
Flash memory
Version
R4F2153 512 Kbytes 40 Kbytes