Datasheet

Rev. 3.00 Sep. 28, 2009 Page xxxiii of xxxiv

REJ09B0384-0300

Section 20 Boundary Scan (JTAG)

Table 20.1 Pin Configuration.................................................................................................. 607

Table 20.2 JTAG Register Serial Transfer.............................................................................. 608

Table 20.3 Correspondence between Pins and Boundary Scan Register ................................ 611

Section 21 Clock Pulse Generator

Table 21.1 Damping Resistance Values ................................................................................. 626

Table 21.2 Crystal Resonator Parameters............................................................................... 627

Table 21.3 Ranges of Multiplied Clock Frequency ................................................................ 628

Section 22 Power-Down Modes

Table 22.1 Operating Frequency and Wait Time.................................................................... 634

Table 22.2 LSI Internal States in Each Mode ......................................................................... 640

Section 24 Electrical Characteristics

Table 24.1 Absolute Maximum Ratings ................................................................................. 673

Table 24.2 DC Characteristics (1) .......................................................................................... 674

Table 24.2 DC Characteristics (2) .......................................................................................... 676

Table 24.3 Permissible Output Currents................................................................................. 677

Table 24.4 Clock Timing........................................................................................................ 679

Table 24.5 External Clock Input Conditions .......................................................................... 680

Table 24.6 Subclock Input Conditions.................................................................................... 680

Table 24.7 Control Signal Timing .......................................................................................... 683

Table 24.8 Timing of On-Chip Peripheral Modules ............................................................... 685

Table 24.9 I

C Bus Timing ..................................................................................................... 688

Table 24.10 LPC Module Timing............................................................................................. 689

Table 24.11 JTAG Timing........................................................................................................ 691

Table 24.12 A/D Conversion Characteristics

(AN7 to AN0 Input: 80/160-State Conversion).................................................... 693

Table 24.13 Flash Memory Characteristics

(100 Programming/Erasing Cycles Specification)................................................ 694

Table 24.14 Flash Memory Characteristics

(1,000 Programming/Erasing Cycles Specification)............................................. 695

Appendix

Table A.1 I/O Port States in Each Processing State............................................................... 697