Datasheet

Section 13 Serial Communication Interface (SCI)
Rev. 3.00 Sep. 28, 2009 Page 312 of 710
REJ09B0384-0300
13.9.4 Receive Error Flags and Transmit Operations (Clock Synchronous Mode Only)
Transmission cannot be started when a receive error flag (ORER, FER, or RER) in SSR is set to 1,
even if the TDRE flag in SSR is cleared to 0. Be sure to clear the receive error flags to 0 before
starting transmission. Note also that the receive error flags cannot be cleared to 0 even if the RE
bit in SCR is cleared to 0.
13.9.5 Relation between Writing to TDR and TDRE Flag
Data can be written to TDR irrespective of the TDRE flag status in SSR. However, if the new data
is written to TDR when the TDRE flag is 0, that is, when the previous data has not been
transferred to TSR yet, the previous data in TDR is lost. Be sure to write transmit data to TDR
after verifying that the TDRE flag is set to 1.
13.9.6 Restrictions on Using DTC
When the external clock source is used as a synchronization clock, update TDR by the DTC and
wait for at least five φ clock cycles before allowing the transmit clock to be input. If the transmit
clock is input within four clock cycles after TDR modification, the SCI may malfunction (figure
13.33).
When using the DTC to read RDR, be sure to set the receive end interrupt source (RXI) as a DTC
activation source.
t
D0
LSB
Serial data
SCK
D1 D3 D4 D5D2 D6 D7
Note: When external clock is supplied, t must be more than four clock cycles.
TDRE
Figure 13.33 Sample Transmission using DTC in Clock Synchronous Mode