Datasheet

Rev. 3.00 Sep. 28, 2009 Page xxxii of xxxiv
REJ09B0384-0300
Section 16 LPC Interface (LPC)
Table 16.1 Pin Configuration.................................................................................................. 407
Table 16.2 LADR1, LADR2 Initial Values ............................................................................ 420
Table 16.3 Host Register Selection......................................................................................... 420
Table 16.4 Slave Selection Internal Registers ........................................................................ 420
Table 16.5 LPC I/O Cycle ...................................................................................................... 467
Table 16.6 Scope of Initialization in Each LPC Interface Mode ............................................ 474
Table 16.7 Serialized Interrupt Transfer Cycle Frame Configuration .................................... 477
Table 16.8 Receive Complete Interrupts and Error Interrupt.................................................. 479
Table 16.9 HIRQ Setting and Clearing Conditions when LPC Channels are Used................ 481
Table 16.10 Host Address Example.......................................................................................... 484
Section 17 A/D Converter
Table 17.1 Pin Configuration.................................................................................................. 487
Table 17.2 Analog Input Channels and Corresponding ADDR Registers.............................. 489
Table 17.3 A/D Conversion Characteristics (Single Mode) ................................................... 498
Table 17.4 A/D Conversion Time (Scan Mode)..................................................................... 498
Table 17.5 A/D Converter Interrupt Source............................................................................ 499
Table 17.6 Standard of Analog Pins ....................................................................................... 505
Section 19 Flash Memory
Table 19.1 Comparison of Programming Modes.................................................................... 512
Table 19.2 Pin Configuration.................................................................................................. 517
Table 19.3 Register/Parameter and Target Mode ................................................................... 518
Table 19.4 Parameters and Target Modes............................................................................... 528
Table 19.5 Setting On-Board Programming Mode................................................................. 538
Table 19.6 System Clock Frequency for Automatic-Bit-Rate Adjustment by This LSI......... 540
Table 19.7 Executable MAT................................................................................................... 560
Table 19.8 (1) Useable Area for Programming in User Program Mode................................... 561
Table 19.8 (2) Useable Area for Erasure in User Program Mode............................................. 563
Table 19.8 (3) Useable Area for Programming in User Boot Mode......................................... 565
Table 19.8 (4) Useable Area for Erasure in User Boot Mode .................................................. 567
Table 19.9 Hardware Protection ............................................................................................. 570
Table 19.10 Software Protection .............................................................................................. 571
Table 19.11 Inquiry and Selection Commands......................................................................... 579
Table 19.12 Programming/Erasing Command.......................................................................... 592
Table 19.13 Status Code ........................................................................................................... 601
Table 19.14 Error Code ............................................................................................................ 602