Datasheet

Section 13 Serial Communication Interface (SCI)
Rev. 3.00 Sep. 28, 2009 Page 301 of 710
REJ09B0384-0300
13.7.4 Receive Data Sampling Timing and Reception Margin
Only the internal clock generated by the internal baud rate generator can be used as a
communication clock in smart card interface mode. In this mode, the SCI can operate using a
basic clock with a frequency of 32, 64, 372, or 256 times the bit rate according to the BCP1 and
BCP0 settings (the frequency is always 16 times the bit rate in normal asynchronous mode). At
reception, the falling edge of the start bit is sampled using the internal basic clock in order to
perform internal synchronization. Receive data is sampled at the 16th, 32nd, 186th and 128th
rising edges of the basic clock pulses so that it can be latched at the center of each bit as shown in
figure 13.25. The reception margin here is determined by the following formula.
M = ⏐ (0.5 – ) – (L – 0.5) F – (1 + F) ⏐ × 100 [%]
...
Formula (1)
2N
1
N
⏐
D – 0.5
⏐
M:
N:
D:
L:
F:
Reception margin (%)
Ratio of bit rate to clock (N = 32, 64, 372, 256)
Clock duty (D = 0 to 1.0)
Frame length (L = 10)
Absolute value of clock rate deviation
Assuming values of F = 0, D = 0.5, and N = 372 in formula (1), the reception margin is
determined by the formula below.
M = (0.5 – 1/2 x 372) x 100 [%] = 49.866%