Datasheet

Rev. 3.00 Sep. 28, 2009 Page xxxi of xxxiv

REJ09B0384-0300

Table 11.2 Registers Accessible by TMR_X/TMR_Y ........................................................... 223

Table 11.3 Interrupt Sources of 8-Bit Timers TMR_0, TMR_1, TMR_Y, and TMR_X ....... 228

Table 11.4 Switching of Internal Clocks and TCNT Operation.............................................. 232

Section 12 Watchdog Timer (WDT)

Table 12.1 Pin Configuration.................................................................................................. 237

Table 12.2 WDT Interrupt Source .......................................................................................... 246

Section 13 Serial Communication Interface (SCI)

Table 13.1 Pin Configuration.................................................................................................. 254

Table 13.2 Relationships between N Setting in BRR and Bit Rate B..................................... 267

Table 13.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode)............ 268

Table 13.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) .......................... 268

Table 13.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) ................ 268

Table 13.6 BRR Settings for Various Bit Rates (Clock Synchronous Mode)......................... 269

Table 13.7 Maximum Bit Rate with External Clock Input (Clock Synchronous Mode) ........ 269

Table 13.8 BRR Settings for Various Bit Rates

(Smart Card Interface Mode, n = 0, s = 372) ........................................................ 270

Table 13.9 Maximum Bit Rate for Each Frequency

(Smart Card Interface Mode, S = 372).................................................................. 270

Table 13.10 Serial Transfer Formats (Asynchronous Mode).................................................... 272

Table 13.11 SSR Status Flags and Receive Data Handling ...................................................... 279

Table 13.12 SCI Interrupt Sources............................................................................................ 310

Table 13.13 SCI Interrupt Sources............................................................................................ 310

Section 15 I

C Bus Interface (IIC)

Table 15.1 Pin Configuration.................................................................................................. 330

Table 15.2 Transfer Format .................................................................................................... 334

Table 15.3 I

C bus Transfer Rate (1) ...................................................................................... 338

Table 15.3 I

C bus Transfer Rate (2) ...................................................................................... 339

Table 15.4 Flags and Transfer States (Master Mode) ............................................................. 346

Table 15.5 Flags and Transfer States (Slave Mode) ............................................................... 347

Table 15.6 Output Data Hold Time ........................................................................................ 358

Table 15.7 ISCMBCR Setting ................................................................................................ 358

Table 15.8 I

C Bus Data Format Symbols .............................................................................. 360

Table 15.9 Examples of Operation Using the DTC ................................................................ 388

Table 15.10 IIC Interrupt Source.............................................................................................. 391

Table 15.11 I

C Bus Timing (SCL and SDA Outputs) ............................................................. 392

Table 15.12 Permissible SCL Rise Time (t

) Values................................................................ 393

Table 15.13 I

C Bus Timing (with Maximum Influence of t

) ............................................. 395