Datasheet

Section 13 Serial Communication Interface (SCI)
Rev. 3.00 Sep. 28, 2009 Page 269 of 710
REJ09B0384-0300
Table 13.6 BRR Settings for Various Bit Rates (Clock Synchronous Mode)
Operating Frequency φ (MHz)
20 24
Bit
Rate
(bit/s)
n N n N
110
250
500 ⎯ ⎯ ⎯ ⎯
1k ⎯ ⎯ ⎯ ⎯
2.5k 2 124 2 149
5k 1 249 2 74
10k 1 124 1 149
25k 0 199 0 239
50k 0 99 0 119
100k 0 49 0 59
250k 0 19 0 23
500k 0 9 0 11
1M 0 4 0 5
2.5M 0 1
5M 0 0*
[Legend]
⎯ : Can be set, but there will be a degree of error.
*: Continuous transfer or reception is not possible.
Table 13.7 Maximum Bit Rate with External Clock Input (Clock Synchronous Mode)
φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s)
20 3.3333 3333333.3
25 4.1667 4166666.7