Datasheet

Rev. 3.00 Sep. 28, 2009 Page xxviii of xxxiv
REJ09B0384-0300
Section 21 Clock Pulse Generator
Figure 21.1 Block Diagram of Clock Pulse Generator............................................................. 625
Figure 21.2 Typical Connection to Crystal Resonator ............................................................. 626
Figure 21.3 Equivalent Circuit of Crystal Resonator ............................................................... 626
Figure 21.4 Example of External Clock Input ......................................................................... 627
Figure 21.5 Note on Board Design of Oscillation Circuit Section........................................... 629
Section 22 Power-Down Modes
Figure 22.1 Mode Transition Diagram..................................................................................... 639
Figure 22.2 Medium-Speed Mode Timing............................................................................... 642
Figure 22.3 Software Standby Mode Application Example..................................................... 644
Figure 22.4 Hardware Standby Mode Timing.......................................................................... 645
Section 24 Electrical Characteristics
Figure 24.1 Darlington Transistor Drive Circuit (Example).................................................... 677
Figure 24.2 LED Drive Circuit (Example)............................................................................... 678
Figure 24.3 Output Load Circuit.............................................................................................. 679
Figure 24.4 System Clock Timing ........................................................................................... 681
Figure 24.5 Oscillation Stabilization Timing........................................................................... 681
Figure 24.6 Oscillation Stabilization Timing (Exiting Software Standby Mode).................... 681
Figure 24.7 External Clock Input Timing ................................................................................ 682
Figure 24.8 Timing of External Clock Output Stabilization Delay Time ................................ 682
Figure 24.9 Subclock Input Timing ......................................................................................... 683
Figure 24.10 Reset Input Timing ............................................................................................... 684
Figure 24.11 Interrupt Input Timing .......................................................................................... 684
Figure 24.12 I/O Port Input/Output Timing ............................................................................... 686
Figure 24.13 PWMX Output Timing ......................................................................................... 686
Figure 24.14 SCK Clock Input Timing...................................................................................... 686
Figure 24.15 SCI Input/Output Timing (Clock Synchronous Mode)......................................... 686
Figure 24.16 A/D Converter External Trigger Input Timing..................................................... 687
Figure 24.17 WDT Output Timing (RESO)............................................................................... 687
Figure 24.18 I
2
C Bus Interface Input/Output Timing................................................................. 689
Figure 24.19 LPC Interface (LPC) Timing ................................................................................ 690
Figure 24.20 JTAG ETCK Timing ............................................................................................ 691
Figure 24.21 Reset Hold Timing................................................................................................ 692
Figure 24.22 JTAG Input/Output Timing .................................................................................. 692
Figure 24.23 Connection of VCL Capacitor .............................................................................. 696
Appendix
Figure C.1 Package Dimensions (PLBG0112GA-A) ............................................................. 699