Datasheet

Section 13 Serial Communication Interface (SCI)
Rev. 3.00 Sep. 28, 2009 Page 262 of 710
REJ09B0384-0300
13.3.7 Serial Status Register (SSR)
SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. TDRE,
RDRF, ORER, PER, and FER can only be cleared. Some bits in SSR have different functions in
normal mode and smart card interface mode.
• Bit Functions in Normal Serial Communication Interface Mode (when SMIF in SCMR = 0)
Bit Bit Name
Initial
Value R/W Description
7 TDRE 1 R/(W)* Transmit Data Register Empty
Indicates whether TDR contains transmit data.
[Setting conditions]
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR and TDR is
ready for data write
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When a TXI interrupt request is issued allowing DTC to
write data to TDR
6 RDRF 0 R/(W)* Receive Data Register Full
Indicates that receive data is stored in RDR.
[Setting condition]
• When serial reception ends normally and receive data
is transferred from RSR to RDR
[Clearing conditions]
• When 0 is written to RDRF after reading RDRF = 1
• When an RXI interrupt request is issued allowing DTC
to read data from RDR
The RDRF flag is not affected and retains its previous value
when the RE bit in SCR is cleared to 0.