Datasheet

Rev. 3.00 Sep. 28, 2009 Page xxvii of xxxiv
REJ09B0384-0300
Figure 17.4 A/D Conversion Timing ....................................................................................... 497
Figure 17.5 Timing of External Trigger Input ......................................................................... 499
Figure 17.6 A/D Conversion Accuracy Definitions................................................................. 501
Figure 17.7 A/D Conversion Accuracy Definitions................................................................. 501
Figure 17.8 Example of Analog Input Circuit.......................................................................... 502
Figure 17.9 Example of Analog Input Protection Circuit ........................................................ 504
Figure 17.10 Analog Input Pin Equivalent Circuit..................................................................... 505
Section 19 Flash Memory
Figure 19.1 Block Diagram of Flash Memory ......................................................................... 510
Figure 19.2 Mode Transition of Flash Memory....................................................................... 511
Figure 19.3 Flash Memory Configuration................................................................................ 513
Figure 19.4 Block Division of User MAT ............................................................................... 514
Figure 19.5 Overview of User Procedure Program.................................................................. 515
Figure 19.6 System Configuration in Boot Mode .................................................................... 539
Figure 19.7 Automatic-Bit-Rate Adjustment Operation of SCI............................................... 540
Figure 19.8 Overview of Boot Mode State Transition Diagram .............................................. 542
Figure 19.9 Programming/Erasing Overview Flow ................................................................. 543
Figure 19.10 RAM Map When Programming/Erasing is Executed........................................... 544
Figure 19.11 Programming Procedure ....................................................................................... 545
Figure 19.12 Erasing Procedure................................................................................................. 550
Figure 19.13 Repeating Procedure of Erasing and Programming .............................................. 552
Figure 19.14 Procedure for Programming User MAT in User Boot Mode................................ 555
Figure 19.15 Procedure for Erasing User MAT in User Boot Mode.......................................... 557
Figure 19.16 Transitions to Error-Protection State .................................................................... 572
Figure 19.17 Switching between the User MAT and User Boot MAT...................................... 573
Figure 19.18 Boot Program States ............................................................................................. 576
Figure 19.19 Bit-Rate-Adjustment Sequence............................................................................. 577
Figure 19.20 Communication Protocol Format.......................................................................... 578
Figure 19.21 New Bit-Rate Selection Sequence ........................................................................ 589
Figure 19.22 Programming Sequence ........................................................................................ 593
Figure 19.23 Erasure Sequence.................................................................................................. 596
Section 20 Boundary Scan (JTAG)
Figure 20.1 JTAG Block Diagram ........................................................................................... 606
Figure 20.2 TAP Controller State Transitions.......................................................................... 617
Figure 20.3 Reset Signal Circuit Without Reset Signal Interference ....................................... 621
Figure 20.4 Serial Data Input/Output (1) ................................................................................. 622
Figure 20.5 Serial Data Input/Output (2) ................................................................................. 623