Datasheet

Section 12 Watchdog Timer (WDT)
Rev. 3.00 Sep. 28, 2009 Page 248 of 710
REJ09B0384-0300
12.6.2 Conflict between Timer Counter (TCNT) Write and Increment
If a timer counter clock pulse is generated during the T
2
state of a TCNT write cycle, the write
takes priority and the timer counter is not incremented. Figure 12.7 shows this operation.
Address
φ
Internal write signal
TCNT input clock
TCNT
N
M
T
1
T
2
TCNT write cycle
Counter write data
Figure 12.7 Conflict between TCNT Write and Increment
12.6.3 Changing Values of CKS2 to CKS0 Bits
If CKS2 to CKS0 bits in TCSR are written to while the WDT is operating, errors could occur in
the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before
changing the values of CKS2 to CKS0 bits.
12.6.4 Changing Value of PSS Bit
If the PSS bit in TCSR_1 is written to while the WDT is operating, errors could occur in the
operation. Stop the watchdog timer (by clearing the TME bit to 0) before changing the values of
PSS bit.