Datasheet

Section 12 Watchdog Timer (WDT)
Rev. 3.00 Sep. 28, 2009 Page 245 of 710
REJ09B0384-0300
12.4.3 RESO Signal Output Timing
When TCNT overflows in watchdog timer mode, the OVF bit in TCSR is set to 1. When the
RST/NMI bit is 1 here, the internal reset signal is generated for the entire LSI. At the same time,
the low level signal is output from the RESO pin. The timing is shown in figure 12.5.
φ
TCNT H'FF H'00
132 states
518 states
Overflow signal
(internal signal)
OVF
RESO signal
Internal reset
signal
Figure 12.5 Output Timing of RESO Signal
This LSI has retain state pins, which are only initialized by a system reset. The outputs on these
pins are retained even when an internal reset is generated by the overflow signal of the WDT. For
more information, see section 8, I/O Ports.