Datasheet

Rev. 3.00 Sep. 28, 2009 Page xxvi of xxxiv
REJ09B0384-0300
Figure 15.19 Slave Receive Mode Operation Timing Example (2) (MLS = 0, HNDS= 1)....... 376
Figure 15.20 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 0) .............. 377
Figure 15.21 Slave Receive Mode Operation Timing Example (1)
(MLS = ACKB = 0, HNDS = 0)........................................................................... 379
Figure 15.22 Slave Receive Mode Operation Timing Example (2)
(MLS = ACKB = 0, HNDS = 0)........................................................................... 380
Figure 15.23 Sample Flowchart for Slave Transmit Mode ........................................................ 381
Figure 15.24 Slave Transmit Mode Operation Timing Example (MLS = 0) ............................. 383
Figure 15.25 IRIC Setting Timing and SCL Control (1) ........................................................... 384
Figure 15.26 IRIC Setting Timing and SCL Control (2) ........................................................... 385
Figure 15.27 IRIC Setting Timing and SCL Control (3) ........................................................... 386
Figure 15.28 Block Diagram of Noise Canceler ........................................................................ 389
Figure 15.29 Notes on Reading Master Receive Data ............................................................... 397
Figure 15.30 Flowchart for Start Condition Issuance Instruction for Retransmission
and Timing............................................................................................................ 398
Figure 15.31 Stop Condition Issuance Timing........................................................................... 399
Figure 15.32 IRIC Flag Clearing Timing When WAIT = 1....................................................... 400
Figure 15.33 ICDR Register Read and ICCR Register Access Timing
in Slave Transmit Mode........................................................................................ 401
Figure 15.34 TRS Bit Set Timing in Slave Mode ...................................................................... 402
Figure 15.35 Diagram of Erroneous Operation when Arbitration Lost ..................................... 404
Section 16 LPC Interface (LPC)
Figure 16.1 Block Diagram of LPC ......................................................................................... 406
Figure 16.2 Typical LFRAME Timing .................................................................................... 468
Figure 16.3 Abort Mechanism ................................................................................................. 468
Figure 16.4 SMIC Write Transfer Flow................................................................................... 469
Figure 16.5 SMIC Read Transfer Flow.................................................................................... 470
Figure 16.6 BT Write Transfer Flow ....................................................................................... 471
Figure 16.7 BT Read Transfer Flow ........................................................................................ 472
Figure 16.8 Power-Down State Termination Timing............................................................... 475
Figure 16.9 SERIRQ Timing ................................................................................................... 476
Figure 16.10 HIRQ Flowchart (Example of Channel 1) ............................................................ 482
Section 17 A/D Converter
Figure 17.1 Block Diagram of the A/D Converter................................................................... 486
Figure 17.2 Example of A/D Converter Operation
(When Channel 1 is Selected in Single Mode) ..................................................... 494
Figure 17.3 Example of A/D Converter Operation
(When Channels AN0 to AN3 are Selected in Scan Mode) ................................. 495