Datasheet

Section 12 Watchdog Timer (WDT)
Rev. 3.00 Sep. 28, 2009 Page 239 of 710
REJ09B0384-0300
Bit Bit Name
Initial
Value
R/W Description
2 to 0 CKS2 to
CKS0
All 0 R/W Clock Select 2 to 0
Select the clock to be input to TCNT. The overflow period
for φ = 25 MHz is enclosed in parentheses.
000: φ/2 (frequency: 20.48 μs)
001: φ/64 (frequency: 655.36 μs)
010: φ/128 (frequency: 1.311 ms)
011: φ/512 (frequency: 5.243 ms)
100: φ/2048 (frequency: 20.97 ms)
101: φ/8192 (frequency: 83.89 ms)
110: φ/32768 (frequency: 335.5 ms)
111: φ/131072 (frequency: 1.34 s)
Note: * Only 0 can be written to clear the flag.