Datasheet

Section 12 Watchdog Timer (WDT)
Rev. 3.00 Sep. 28, 2009 Page 238 of 710
REJ09B0384-0300
12.3.2 Timer Control/Status Register (TCSR)
TCSR selects the clock source to be input to TCNT, and the timer mode.
• TCSR_0
Bit Bit Name
Initial
Value
R/W Description
7 OVF 0 R/(W)* Overflow Flag
Indicates that TCNT has overflowed (changes from H'FF
to H'00).
[Setting conditions]
• When TCNT overflows (changes from H'FF to H'00)
• When internal reset request generation is selected in
watchdog timer mode, OVF is cleared automatically by
the internal reset.
[Clearing conditions]
• When TCSR is read when OVF = 1, then 0 is written to
OVF
• When 0 is written to TME
6 WT/IT 0 R/W Timer Mode Select
Selects whether the WDT is used as a watchdog timer or
interval timer.
0: Interval timer mode
1: Watchdog timer mode
5 TME 0 R/W Timer Enable
When this bit is set to 1, TCNT starts counting.
When this bit is cleared, TCNT stops counting and is
initialized to H'00.
4 ⎯ 0 R/W Reserved
The initial value should not be changed.
3 RST/NMI 0 R/W Reset or NMI
Selects to request an internal reset or an NMI interrupt
when TCNT has overflowed.
0: An NMI interrupt is requested
1: An internal reset is requested