Datasheet

Section 12 Watchdog Timer (WDT)
Rev. 3.00 Sep. 28, 2009 Page 237 of 710
REJ09B0384-0300
12.2 Input/Output Pins
The WDT has the pins listed in table 12.1.
Table 12.1 Pin Configuration
Name Symbol I/O Function
Reset output pin RESO Output Outputs the counter overflow signal in
watchdog timer mode
External sub-clock input
pin
EXCL Input Inputs the clock pulses to the WDT_1
prescaler counter
12.3 Register Descriptions
The WDT has the following registers. To prevent accidental overwriting, TCSR and TCNT have
to be written to in a method different from normal registers. For details, see section 12.6.1, Notes
on Register Access. For details on the system control register, see section 3.2.2, System Control
Register (SYSCR).
• Timer counter (TCNT)
• Timer control/status register (TCSR)
12.3.1 Timer Counter (TCNT)
TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 when the TME bit in
timer control/status register (TCSR) is cleared to 0.