Datasheet

Rev. 3.00 Sep. 28, 2009 Page xxv of xxxiv
REJ09B0384-0300
Figure 13.35 Pin States during Transmission in Asynchronous Mode (Internal Clock) ............ 314
Figure 13.36 Pin States during Transmission in Clock Synchronous Mode (Internal Clock)... 315
Figure 13.37 Sample Flowchart for Mode Transition during Reception.................................... 316
Figure 13.38 Switching from SCK Pins to Port Pins ................................................................. 317
Figure 13.39 Prevention of Low Pulse Output at Switching from SCK Pins to Port Pins ......... 318
Section 14 CRC Operation Circuit (CRC)
Figure 14.1 Block Diagram of CRC Operation Circuit............................................................ 319
Figure 14.2 LSB-First Data Transmission ............................................................................... 321
Figure 14.3 MSB-First Data Transmission .............................................................................. 322
Figure 14.4 LSB-First Data Reception..................................................................................... 323
Figure 14.5 MSB-First Data Reception.................................................................................... 324
Figure 14.6 LSB-First and MSB-First Transmit Data.............................................................. 325
Section 15 I
2
C Bus Interface (IIC)
Figure 15.1 Block Diagram of I
2
C Bus Interface ..................................................................... 328
Figure 15.2 I
2
C Bus Interface Connections (Example: This LSI as Master) ............................ 329
Figure 15.3 I
2
C Bus Data Formats (I
2
C Bus Formats).............................................................. 359
Figure 15.4 I
2
C Bus Data Formats (Serial Formats)................................................................. 359
Figure 15.5 I
2
C Bus Timing ..................................................................................................... 360
Figure 15.6 Sample Flowchart for IIC Initialization ................................................................ 361
Figure 15.7 Sample Flowchart for Operations in Master Transmit Mode ............................... 362
Figure 15.8 Operation Timing Example in Master Transmit Mode (MLS = WAIT = 0) ........ 364
Figure 15.9 Stop Condition Issuance Operation Timing Example
in Master Transmit Mode (MLS = WAIT = 0)..................................................... 365
Figure 15.10 Sample Flowchart for Operations in Master Receive Mode (HNDS = 1) ............ 366
Figure 15.11 Master Receive Mode Operation Timing Example
(MLS = WAIT = 0, HNDS = 1)............................................................................ 368
Figure 15.12 Stop Condition Issuance Timing Example in Master Receive Mode
(MLS = WAIT = 0, HNDS = 1)............................................................................ 368
Figure 15.13 Sample Flowchart for Operations in Master Receive Mode
(receiving multiple bytes) (WAIT = 1)................................................................. 369
Figure 15.14 Sample Flowchart for Operations in Master Receive Mode
(receiving a single byte) (WAIT = 1).................................................................... 370
Figure 15.15 Master Receive Mode Operation Timing Example
(MLS = ACKB = 0, WAIT = 1) ........................................................................... 372
Figure 15.16 Stop Condition Issuance Timing Example in Master Receive Mode
(MLS = ACKB = 0, WAIT = 1) ........................................................................... 373
Figure 15.17 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 1)............... 374
Figure 15.18 Slave Receive Mode Operation Timing Example (1) (MLS = 0, HNDS= 1) ....... 376