Datasheet

Section 11 8-Bit Timer (TMR)
Rev. 3.00 Sep. 28, 2009 Page 231 of 710
REJ09B0384-0300
11.6.3 Conflict between TCOR Write and Compare-Match
If a compare-match occurs during the T
2
state of a TCOR write cycle as shown in figure 11.9, the
TCOR write takes priority and the compare-match signal is disabled.
φ
Address TCOR address
Internal write signal
TCNT
TCOR N M
T
1
T
2
TCOR write cycle by CPU
TCOR write data
N N + 1
Compare-match signal
Disabled
Figure 11.9 Conflict between TCOR Write and Compare-Match