Datasheet

Section 11 8-Bit Timer (TMR)
Rev. 3.00 Sep. 28, 2009 Page 230 of 710
REJ09B0384-0300
11.6.2 Conflict between TCNT Write and Increment
If a TCNT input clock is generated during the T
2
state of a TCNT write cycle as shown in figure
11.8, the write takes priority and the counter is not incremented.
φ
Address TCNT address
Internal write signal
TCNT input clock
TCNT N M
T
1
T
2
TCNT write cycle by CPU
Counter write data
Figure 11.8 Conflict between TCNT Write and Increment