Datasheet

Section 11 8-Bit Timer (TMR)
Rev. 3.00 Sep. 28, 2009 Page 219 of 710
REJ09B0384-0300
11.2.5 Timer Control/Status Register (TCSR)
TCSR indicates the status flags and controls compare-match output. About the TCSR_Y and
TCSR_X accesses see section 11.2.6, Timer Connection Register S (TCONRS).
• TCSR_0
Bit Bit Name
Initial
Value
R/W Description
7 CMFB 0 R/(W)* Compare-Match Flag B
[Setting condition]
When the values of TCNT_0 and TCORB_0 match
[Clearing condition]
Read CMFB when CMFB = 1, then write 0 in CMFB
6 CMFA 0 R/(W)* Compare-Match Flag A
[Setting condition]
When the values of TCNT_0 and TCORA_0 match
[Clearing condition]
Read CMFA when CMFA = 1, then write 0 in CMFA
5 OVF 0 R/(W)* Timer Overflow Flag
[Setting condition]
When TCNT_0 overflows from H′FF to H′00
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
4 ADTE 0 R/W A/D Trigger Enable
Selects whether the A/D conversion start request on
compare match A is enabled or disabled.
0: A/D conversion start request is disabled
1: A/D conversion start request is enabled
3 to 0 ⎯ All 1 R Reserved
These bits are always read as 1 and cannot be modified.
Note: * Only 0 can be written to clear the flag.