Datasheet

Section 11 8-Bit Timer (TMR)
Rev. 3.00 Sep. 28, 2009 Page 218 of 710
REJ09B0384-0300
Table 11.1 (3) Clock Input to TCNT and Count Condition (TMR_Y, TMR_X, Common)
TCR
Channel CKS2 CKS1 CKS0 Description
0 0 0 Disables clock input
0 0 1 Increments at falling edge of internal clock φ/4
0 1 0 Increments at falling edge of internal clock φ/256
0 1 1 Increments at falling edge of internal clock φ/2048
TMR_Y
1 0 0 Setting prohibited
0 0 0 Disables clock input
0 0 1 Increments at falling edge of internal clock φ
0 1 0 Increments at falling edge of internal clock φ/2
0 1 1 Increments at falling edge of internal clock φ/4
TMR_X
1 0 0 Setting prohibited
1 0 1 Setting prohibited Common
1 1 0 Setting prohibited
1 1 1 Setting prohibited