Datasheet

Section 11 8-Bit Timer (TMR)
Rev. 3.00 Sep. 28, 2009 Page 217 of 710
REJ09B0384-0300
Table 11.1 (1) Clock Input to TCNT and Count Condition (TMR_0)
TCR STCR
CKS2 CKS1 CKS0 ICKS0 Description
0 0 0 ⎯ Disables clock input
0 0 1 0 Increments at falling edge of internal clock φ/8
0 0 1 1 Increments at falling edge of internal clock φ/2
0 1 0 0 Increments at falling edge of internal clock φ/64
0 1 0 1 Increments at falling edge of internal clock φ/32
0 1 1 0 Increments at falling edge of internal clock φ/1024
0 1 1 1 Increments at falling edge of internal clock φ/256
1 0 0 ⎯ Increments at overflow signal from TCNT_1
Table 11.1 (2) Clock Input to TCNT and Count Condition (TMR_1)
TCR STCR
CKS2 CKS1 CKS0 ICKS1 Description
0 0 0 ⎯ Disables clock input
0 0 1 0 Increments at falling edge of internal clock φ/8
0 0 1 1 Increments at falling edge of internal clock φ/2
0 1 0 0 Increments at falling edge of internal clock φ/64
0 1 0 1 Increments at falling edge of internal clock φ/128
0 1 1 0 Increments at falling edge of internal clock φ/1024
0 1 1 1 Increments at falling edge of internal clock φ/2048
1 0 0 ⎯ Increments at compare-match A from TCNT_0