Datasheet

Rev. 3.00 Sep. 28, 2009 Page xxiii of xxxiv
REJ09B0384-0300
Section 10 16-Bit Free-Running Timer (FRT)
Figure 10.1 Block Diagram of 16-Bit Free-Running Timer..................................................... 194
Figure 10.2 Increment Timing with Internal Clock Source...................................................... 201
Figure 10.3 Timing of Output Compare A Output................................................................... 201
Figure 10.4 Clearing of FRC by Compare-Match A Signal..................................................... 202
Figure 10.5 Timing of Output Compare Flag (OCFA or OCFB) Setting ................................ 202
Figure 10.6 Timing of Overflow Flag (OVF) Setting .............................................................. 203
Figure 10.7 OCRA Automatic Addition Timing...................................................................... 204
Figure 10.8 Conflict between FRC Write and Clear ................................................................ 205
Figure 10.9 Conflict between FRC Write and Increment......................................................... 206
Figure 10.10 Conflict between OCR Write and Compare-Match
(When Automatic Addition Function is Not Used) .............................................. 207
Figure 10.11 Conflict between OCR Write and Compare-Match
(When Automatic Addition Function is Used) ..................................................... 208
Section 11 8-Bit Timer (TMR)
Figure 11.1 Block Diagram of 8-Bit Timer (TMR_0 and TMR_1) ......................................... 212
Figure 11.2 Block Diagram of 8-Bit Timer (TMR_Y and TMR_X) ....................................... 213
Figure 11.3 Count Timing for Internal Clock Input ................................................................. 224
Figure 11.4 Timing of CMF Setting at Compare-Match.......................................................... 225
Figure 11.5 Timing of Counter Clear by Compare-Match....................................................... 225
Figure 11.6 Timing of OVF Flag Setting................................................................................. 226
Figure 11.7 Conflict between TCNT Write and Counter Clear ............................................... 229
Figure 11.8 Conflict between TCNT Write and Increment...................................................... 230
Figure 11.9 Conflict between TCOR Write and Compare-Match............................................ 231
Section 12 Watchdog Timer (WDT)
Figure 12.1 Block Diagram of WDT........................................................................................ 236
Figure 12.2 Watchdog Timer Mode (RST/NMI = 1) Operation .............................................. 243
Figure 12.3 Interval Timer Mode Operation ............................................................................ 243
Figure 12.4 OVF Flag Set Timing ........................................................................................... 244
Figure 12.5 Output Timing of RESO Signal............................................................................ 245
Figure 12.6 Writing to TCNT and TCSR (WDT_0) ................................................................ 247
Figure 12.7 Conflict between TCNT Write and Increment...................................................... 248
Figure 12.8 Sample Circuit for Resetting the System by the RESO Signal ............................. 249
Section 13 Serial Communication Interface (SCI)
Figure 13.1 Block Diagram of SCI_1 and SCI_3..................................................................... 253
Figure 13.2 Data Format in Asynchronous Communication
(Example with 8-Bit Data, Parity, Two Stop Bits) ............................................... 271