Datasheet

Section 10 16-Bit Free-Running Timer (FRT)
Rev. 3.00 Sep. 28, 2009 Page 208 of 710
REJ09B0384-0300
φ
Address
OCRAR (OCRAF)
address
Internal write signal
Compare-match signal
FRC
Automatic addition is not performed
because compare-match signals are disabled.
Disabled
OCR
N
N N+1
OCRAR (OCRAF)
Old data
New data
Figure 10.11 Conflict between OCR Write and Compare-Match
(When Automatic Addition Function is Used)
10.5.4 Switching of Internal Clock and FRC Operation
When the internal clock is changed, the changeover may source FRC to increment. This depends
on the time at which the clock is switched (bits CKS1 and CKS0 are rewritten), as shown in table
10.2.
When an internal clock is used, the FRC clock is generated on detection of the falling edge of the
internal clock scaled from the system clock (φ). If the clock is changed when the old source is high
and the new source is low, as in case no. 3 in table 10.2, the changeover is regarded as a falling
edge that triggers the FRC clock, and FRC is incremented. Switching between an internal clock
and external clock can also source FRC to increment.