Datasheet

Section 10 16-Bit Free-Running Timer (FRT)
Rev. 3.00 Sep. 28, 2009 Page 205 of 710
REJ09B0384-0300
10.5 Usage Notes
10.5.1 Conflict between FRC Write and Clear
If an internal counter clear signal is generated during the state after an FRC write cycle, the clear
signal takes priority and the write is not performed. Figure 10.8 shows the timing for this type of
conflict.
φ
Address FRC address
Internal write
signal
Counter clear
signal
FRC N
H'0000
T
1
T
2
Write cycle of FRC
Figure 10.8 Conflict between FRC Write and Clear