Datasheet

Section 10 16-Bit Free-Running Timer (FRT)
Rev. 3.00 Sep. 28, 2009 Page 204 of 710
REJ09B0384-0300
10.3.6 Automatic Addition Timing
When the OCRAMS bit in TOCR is set to 1, the contents of OCRAR and OCRAF are
automatically added to OCRA alternately, and when an OCRA compare-match occurs a write to
OCRA is performed. Figure 10.7 shows the OCRA write timing.
Compare-match
signal
OCRAR, OCRAF
A
OCRA N N + A
FRC N N +1
φ
Figure 10.7 OCRA Automatic Addition Timing
10.4 Interrupt Sources
The free-running timer can request three interrupts: OCIA, OCIB, and FOVI. Each interrupt can
be enabled or disabled by an enable bit in TIER. Independent signals are sent to the interrupt
controller for each interrupt. Table 10.1 lists the sources and priorities of these interrupts.
The OCIA and OCIB interrupts can be used as the on-chip DTC activation sources.
Table 10.1 FRT Interrupt Sources
Interrupt Interrupt Source Interrupt Flag DTC Activation Priority
OCIA Compare match of OCRA OCFA Possible High
OCIB Compare match of OCRB OCFB Possible
FOVI Overflow of FRC OVF Not possible Low