Datasheet

Rev. 3.00 Sep. 28, 2009 Page xxii of xxxiv
REJ09B0384-0300
Figure 5.6 Flowchart of Procedure Up to Interrupt Acceptance
in Interrupt Control Mode 1................................................................................... 84
Figure 5.7 Interrupt Exception Handling ................................................................................. 86
Figure 5.8 Interrupt Control for DTC....................................................................................... 88
Figure 5.9 Conflict between Interrupt Generation and Disabling ............................................ 90
Section 6 Bus Controller (BSC)
Figure 6.1 Block Diagram of Bus Controller........................................................................... 93
Section 7 Data Transfer Controller (DTC)
Figure 7.1 Block Diagram of DTC........................................................................................... 98
Figure 7.2 Block Diagram of DTC Activation Source Control.............................................. 109
Figure 7.3 DTC Register Information Location in Address Space ........................................ 110
Figure 7.4 Correspondence between DTC Vector Address and Register Information .......... 111
Figure 7.5 DTC Operation Flowchart .................................................................................... 112
Figure 7.6 Memory Mapping in Normal Transfer Mode ....................................................... 113
Figure 7.7 Memory Mapping in Repeat Transfer Mode ........................................................ 114
Figure 7.8 Memory Mapping in Block Transfer Mode.......................................................... 115
Figure 7.9 Chain Transfer Operation ..................................................................................... 116
Figure 7.10 DTC Operation Timing
(Example in Normal Transfer Mode or Repeat Transfer Mode) .......................... 117
Figure 7.11 DTC Operation Timing
(Example of Block Transfer Mode, with Block Size of 2) .................................. 118
Figure 7.12 DTC Operation Timing (Example of Chain Transfer).......................................... 118
Section 8 I/O Ports
Figure 8.1 Noise Canceler Circuit.......................................................................................... 135
Figure 8.2 Noise Canceler Operation..................................................................................... 136
Figure 8.3 Noise Canceler Circuit.......................................................................................... 140
Figure 8.4 Noise Canceler Operation..................................................................................... 141
Section 9 14-Bit PWM Timer (PWMX)
Figure 9.1 PWMX (D/A) Block Diagram.............................................................................. 177
Figure 9.2 PWMX (D/A) Operation ...................................................................................... 185
Figure 9.3 Output Waveform (OS = 0, DADR corresponds to T
L
) ........................................ 188
Figure 9.4 Output Waveform (OS = 1, DADR corresponds to T
H
)........................................ 189
Figure 9.5 D/A Data Register Configuration when CFS = 1 ................................................. 189
Figure 9.6 Output Waveform when DADR = H'0207 (OS = 1)............................................. 190