Datasheet

Section 10 16-Bit Free-Running Timer (FRT)
Rev. 3.00 Sep. 28, 2009 Page 202 of 710
REJ09B0384-0300
10.3.3 FRC Clear Timing
FRC can be cleared when compare-match A occurs. Figure 10.4 shows the timing of this
operation.
φ
FRC N H'0000
Compare-match
A signal
Figure 10.4 Clearing of FRC by Compare-Match A Signal
10.3.4 Timing of Output Compare Flag (OCF) Setting
The output compare flag, OCFA or OCFB, is set to 1 by a compare-match signal generated when
the FRC value matches the OCRA or OCRB value. This compare-match signal is generated at the
last state in which the two values match, just before FRC increments to a new value. When the
FRC and OCRA or OCRB value match, the compare-match signal is not generated until the next
cycle of the clock source. Figure 10.5 shows the timing of setting the OCFA or OCFB flag.
Compare-match
signal
OCFA, OCFB
OCRA, OCRB N
FRC N N + 1
φ
Figure 10.5 Timing of Output Compare Flag (OCFA or OCFB) Setting